MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 768

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Enhanced Three-Speed Ethernet Controllers
15.5.3.3.2
The eTSEC writes to this register under the following conditions:
Writing 1 to any bit of this register clears it. Software should clear the QHLT bit to take eTSEC’s receiver
function out of halt state for the associated queue.
register.
15-50
Offset eTSEC1:0x2_4304; eTSEC2:0x2_5304
Reset
Reset
Bits
26
27
28
29
30
31
•
•
•
W
W
R
R
A frame interrupt event occurred on one or more RxBD rings
The receiver runs out of descriptors due to a busy condition on a RxBD ring
The receiver was halted because an error condition was encountered while receiving a frame
16
0
BC_REJ
PROM
EMEN
Name
RSF
—
—
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Receive Status Register (RSTAT)
Reserved
Broadcast frame reject. If this bit is set, frames with DA (destination address) = FFFF_FFFF_FFFF are
rejected unless RCTRL[PROM] is set. If both BC_REJ and RCTRL[PROM] are set, then frames with
broadcast DA are accepted and the M (MISS) bit is set in the receive BD.
Promiscuous mode. All Ethernet frames, regardless of destination address, are accepted.
Receive short frame mode. When set, enables the reception of frames shorter than 64 bytes.
0 Ethernet frames less than 64B in length are silently dropped.
1) Frames more than 16B and less than 64B in length are accepted upon a DA match.
Note that frames less than or equal to 16B in length are always silently dropped.
Exact match MAC address enable. If this bit is set, the MAC01ADDR1–MAC15ADDR1 and
MAC01ADDR2–MAC15ADDR2 registers are recognized as containing MAC addresses aliasing the
MAC’s station address. Setting this bit therefore allows eTSEC to receive Ethernet frames having a
destination address matching one of these 15 addresses.
Reserved
—
—
Table 15-27. RCTRL Field Descriptions (continued)
Figure 15-23. RSTAT Register Definition
23
7
QHLT0 QHLT1 QHLT2 QHLT3 QHLT4 QHLT5 QHLT6 QHLT7
RXF0
w1c
w1c
24
8
Figure 15-23
All zeros
All zeros
RXF1
w1c
w1c
25
9
Description
RXF2
w1c
w1c
10
26
describes the definition for the RSTAT
RXF3
w1c
w1c
11
27
RXF4
w1c
w1c
12
28
RXF5
Freescale Semiconductor
w1c
w1c
13
29
RXF6
w1c
w1c
14
30
Access: w1c
RXF7
w1c
w1c
15
31