MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 425

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Figure 9-20
Figure 9-21
Figure 9-22
four 8M × 8 DDR modules for a total of 128 Mbytes of system memory. Certain address and control lines
may require buffering. Analysis of the device’s AC timing specifications, desired memory operating
frequency, capacitive loads, and board routing loads can assist the system designer in deciding signal
buffering requirements. The DDR memory controller drives 15 address pins, but in this example the DDR
SDRAM devices use only 12 bits.
Freescale Semiconductor
shows an example DDR SDRAM configuration with four logical banks.
shows some typical signal connections.
shows an example DDR SDRAM configuration with two physical banks each comprised of
MCS, MRAS, MCAS, MWE
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Figure 9-20. Typical Dual Data Rate SDRAM Internal Organization
BANK ADDR
CKE, MCK, MCK
COMMAND:
ADDR
MRAS
MCAS
‘SUB’
MWE
MCS
MCK
MCK
Figure 9-21. Typical DDR SDRAM Interface Signals
CKE
BA1,BA0
DM
ADDR
DQM
13
2
SDRAM
Control
A[12:0]
BA[1:0]
Write Enable
64M x 1 Byte
Command
Bus
CK
512 Mbit
Data-Out Registers
Logical
Bank 0
DQ[7:0]
DQS
Logical
Bank 1
Read Data Latch
MUX, MASK,
Data Bus
8
Logical
Bank 2
Data-In Registers
DATA
DATA
STROBE
Logical
Bank 3
DDR Memory Controller
9-31