MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 625

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

13.4
The following sections discuss the operation of the PCI controller.
13.4.1
The PCI bus arbitration approach is access-based. Bus masters must arbitrate for each access performed
on the bus. PCI uses a central arbitration scheme where each master has its own unique request (REQn)
output and grant (GNTn) input signal. A simple request-grant handshake is used to gain access to the bus.
Arbitration for the bus occurs during the previous access so that no PCI bus cycles are consumed waiting
for arbitration (except when the bus is idle).
Freescale Semiconductor
21–16
14–13
12–9
Bits
7–4
1–0
22
15
8
3
2
Functional Description
PCI Bus Arbitration
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
No_Soft_Reset
Power_State
PME_Status
Data_Select
Data_Scale
PME_En
B2_B3
Name
—
—
—
Table 13-44. PCIPMR1 Field Descriptions (continued)
The state of this bit determines what will happen as a direct result of programming the
function to D3_hot.
0 Indicates that when the bridge function is programmed to D3_hot, its secondary bus will
1 Indicates that when the bridge function is programed to D3_hot, its secondary bus’s PCI
This bit only meaningful if bit 16 (BPCC_En) is set.
Note: This bit field is not implemented, only required for all PCI-to-PCI Bridge
Reserved
This bit set when the PCI controller would normally assert PME# signal independent of the
state of the PME_En bit. Writing a value of one to this bit will clear it and cause the PCI
controller to stop asserting a PME# signal.
0 Default
1 If (Wake_Up & PME_En)
The scale factor to be used when interpreting the value of the data register
Selects which data is to be reported through the data register and Data_Scale field
Enables the function to assert PME#
0 Disables the function to assert PME#
1 Enables the function to assert PME#
Reserved
This bit field indicates whether an internal reset occurs during the transition from D3_hot to
D0.
0 The Power_State command performs an internal reset.
1 The Power_State command does not perform an internal reset.
Reserved
Determines the current power state of the PCI controller and sets the controller into a new
power state.
The power state definition is as follows:
00 D0 supports all PCI function.
01 D1 disables the inbound memory space, bus mastering and functional interrupt request.
10 D2 disables the inbound memory space, bus mastering and functional interrupt request.
11 D3_hot disables the inbound memory space, bus mastering and functional interrupt
have its power removed (B3).
clock will be stopped (B2).
request.
Description
PCI Bus Interface
13-43