MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 497

Manufacturer Part Number

MPC8313CZQADDC

Microprocessors - MPU 8313 REV2.2 PB NO EN EXT

Manufacturer

Freescale Semiconductor

Processor Series

Data Bus Width

Maximum Clock Frequency

Program Memory Size

Data Ram Size

Interface Type

Mounting Style

Package / Case

Number Of Programmable I/os

Number Of Timers

Manufacturer

BOSTOCK HK LIMITED

Part Number:

MPC8313CZQADDC

Manufacturer:

Freescale Semiconductor

The banks selected to work with the GPCM support an option to drive the LCSn signal with different

timings (with respect to the external address/data bus). LCSn can be driven in any of the following ways:

Freescale Semiconductor

Simultaneous with the latched memory address. (This refers to the externally latched address and

not the address timing on LAD. That is, the chip select does not assert during LALE).

One quarter of a clock cycle later (for LCRR[CLKDIV] = 4, 8).

One half of a clock cycle later (for LCRR[CLKDIV] = 2, 4, or 8).

One clock cycle later (for LCRR[CLKDIV] = 4), when OR

Two clock cycles later (for LCRR[CLKDIV] = 2, 4, or 8), when OR

Times in parentheses are specific for the case LCRR[CLKDIV] = 2; other times apply to all CLKDIV values.

Option Register Attributes

Chip-Select Assertion Timing

MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2

Table 10-33. GPCM Write Control Signal Timing (continued)

Signal Timing (LCLK clock cycles)

Enhanced Local Bus Controller