MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 1206

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

M–M
Local bus controller (LBC)
Index-8
address and address space checking, 10-41
address mask field—option registers, 10-11
atomic bus operations, 10-44
block diagram, 10-1
boot chip-select operation, 10-56, 10-69
bus monitor, 10-44
bus turnaround, 10-91
clocks and clock ratios, 10-3
configuration
error handling
external access termination (LGTA), 10-55
features, 10-2
functional description, 10-40
general-purpose chip-select machine (GPCM), 10-45
initialization/application information, 10-88
interrupts
memory map/register definition, 10-7
memory refresh timer prescaler, 10-22
modes of operation, 10-3
overview, 1-14, 10-2
peripherals, 10-88
port sizes, 10-92
register descriptions, 10-9
signals, 10-4
additional address phases (UPM cycles), 10-92
address following read, 10-91
read data following address, 10-91
read-modify-write cycle (parity), 10-92
clock ratio register (LCRR), 10-33
LBC configuration register (LBCR), 10-31
transfer error registers, 10-25–10-30
chip-select and write enable negation timing, 10-50
chip-select assertion timing, 10-49
extended hold time on read accesses, 10-54
GPCM mode
output enable timing, 10-54
programmable wait state configuration, 10-50
relaxed timing, 10-51
timing configuration, 10-46, 10-47, 10-65
transfer error interrupt enable register (LTEIR), 10-28
bus clock and clock ratios, 10-3
GPCM mode, registers, 10-13, 10-15
source ID debug mode, 10-4
UPM mode, registers, 10-18
GPCM timing, 10-90
hierarchy for very high speeds, 10-89
multiplexed address/data, 10-88
by acronym, see Register Index
see also Signals, LBC
registers, 10-13, 10-15
MPC8313E PowerQUICC™ II Pro Integrated Processor Reference Manual, Rev. 2
LOE (LBC GPCM output enable) signal, 10-6
LWE[0:3] (LBC GPCM write enable) signals, 10-5
M
MA[0:14] (DDR address bus) signals, 9-6
MAC functionality, see eTSEC, MAC functionality
Machine check enable, 7-18
Master control register, 14-74
MBA[0:1] (DDR logical bank address) signals, 9-6
MCAS (DDR column address strobe) signal, 9-6
MCK[0:5] (DDR clock output complement) signals, 9-7
MCK[0:5] (DDR clock output) signals, 9-7
MCKE[0:3] (DDR clock enable) signals, 9-8
mcp (machine check processor signal), 8-2
MCS[0:3] (DDR chip select) signals, 9-7
MDEU
UPM interfaces, 10-72–10-102
ZBT SRAM interface, 10-97, 10-102
context registers, 14-38
data size register, 14-32, 14-37
FIFOs, 14-40
interrupt control register, 14-36
interrupt status register, 14-32, 14-35
key registers, 14-39
key size register, 14-32
mode register, 14-28
reset control register, 14-33
block diagram, 10-72
extended hold time (reads), 10-87
programming the UPMs, 10-75
RAM array, 10-78
signal timing, 10-77
synchronous UPWAIT (early transfer acknowledge),
UPM mode
UPM requests, 10-73
address multiplexing, 10-84
byte select signal timing, 10-83
chip select signal timing, 10-82
data timing, 10-85
general purpose signal timing, 10-83
LGPL[0:5] timing (LAST), 10-86
loop control, 10-83
RAM word definition, 10-79
REDO, 10-84
wait mechanism (WAEN), 10-86
registers, 10-18, 10-19
exception requests, 10-75
memory access requests, 10-74
refresh timer requests, 10-74
software requests, 10-75
10-87
Freescale Semiconductor
Index