MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 1186

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Revision History
15.5.3.4.1, 15-50
15.5.3.4.2, 15-51
15.5.3.4.6, 15-57
15.5.3.4.8, 15-59
15.5.3.4.12, 15-63
15.5.3.6.2, 15-69
15.5.3.6.5, 15-73
15.5.3.6.6, 15-73
15.5.3.7.19, 15-89
15.5.3.7.25, 15-92
15.5.3.9, 15-107
15.6.2.10.3, 15-157
A-28
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Parser disabled. Receive frame filer must also be disabled by clearing
RCTRL[FILREN].
Changed RCTRL[FILREN] description (but not bit settings) to the following:
Filer enable, when set, the receive frame filer is enabled. This will file accepted
frames to a particular RxBD ring according to rules defned in the filer table. In this
case, PRSDEP must not be cleared.
Updated register to show that they are w1c (all fields).
Added note to RQFPR[ETY].
In Table 15-39, added the following note for bit TOS:
IPv6 the Traffic Class field is extracted using the IP header definition in RFC
2460. IPv6 headers formed using the earlier RFC 1883 have a different format and
must be handled with software.
Removed register sections (and memory map rows) from MPC8313 product
which only have a 32-bit address space.Using the filer to match ETY does not
work in the case of PPPoe packets, beacuse the PPPoe ethertype in the original
packet, 0x8864, is always overwritten with the PPP protocol field. thus, matches
on ETY == 0x8864 always fail, Instead, software should use PID=1 fields
IP4(ETy = 0x0021) and IP6 (ETY = 0x0057) to distinguish PPPoe session packets
carrying IPv4 and IPv6 datagrams. Other PPP protocols are encoded in the ETY
field, but many of them overlap with real ethertype definitions. Consult IANA and
IEEE for possible ambiguities.
In Table 15-47, added cross-reference to buffer descriptors section to description
of MACCFG2[Huge Frame].
Added the following note to section, Maximum Frame Length Register
(MAXFRM):
If MACCFG[Huge Frame] = 0, the value of this field must be less than or equal
to MRBLR[MRBL] x (minimum number of RxBDs per ring). See Section
15.5.3.6.2, “MAC Configuration 2 Register (MACCFG2),” Section 15.5.3.4.9,
“Maximum Receive Buffer length Register (MRBLR),” and Section 15.6.6.3,
“Receive Buffer Descriptors (RXBD).”
Added a note regarding eTSEC system clock to MgmtClk bit description.
Modified RCSE bit description.
In Table 15-86, added the following note to TBYT[TBYT]:
The value of TBYT may be greater than the actual number of bytes transmitted if
the frame is truncated because it exceeds MAXFRM.
Removed text related to L2 cache.
In Table 15-149, “Interrupt Coalescing Timing Threshold Ranges,
eTSEC frequencies of 266 and 333 MHz with 133 and 166 MHz
information/rows.
Freescale Semiconductor
”
replaced