MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 670

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Security Engine (SEC) 2.2
14.4.1.10 DEU Key Registers (DEUK n )
The DEU uses three write-only key registers (DEUK1, DEUK2, and DEUK3) to perform encryption and
decryption. In single DES mode, only DEUK1 may be written. The value written to DEUK1 is
simultaneously written to DEUK3, auto-enabling the DEU for 112-bit triple DES if the key size register
indicates 2-key 3DES is to be performed (key size = 16 bytes). To operate in 168-bit triple DES, DEUK1
must be written first, followed by a write to DEUK2 and DEUK3.
Reading any of these memory locations generates an address error interrupt.
14.4.1.11 DEU FIFOs
DEU uses the symmetric shared input FIFO/output FIFO pair to hold data before and after the encryption
process. These FIFOs are multiply addressable, but those multiple addresses point only to the appropriate
end of the appropriate FIFO. A write to anywhere in the DEU FIFO address space causes the 64-bit-word
to be pushed onto the shared symmetric input FIFO, and for that FIFO to be configured as reserved for
DEU, and a read from anywhere in the DEU FIFO address space causes a 64-bit-word to be popped off of
the shared symmetric output FIFO. Overflows and underflows caused by reading or writing the shared
symmetric FIFOs are reflected in the DEUISR
14.4.2
Message Digest Execution Unit (MDEU)
This section contains details about the message digest execution unit (MDEU), including modes of
operation, status and control registers, and FIFOs.
Most of the registers described here would not normally be accessed by the host. They are documented
here mainly for debug purposes. In typical operation, the MDEU is used through channel-controlled
access, which means that most reads and writes of MDEU registers are directed by the SEC channel.
Driver software would perform host-controlled register accesses only on a few registers for initial
configuration and error handling.
14.4.2.1
MDEU Mode Register (MDEUMR)
The MDEU mode register (MDEUMR) is used to program the function of the MDEU. Bits 56–63 of the
MDEUMR are specified by the user through the MODE0 or MODE1 field of the descriptor header. The
remaining bits are supplied by the channel and thus are not under direct user control.
The MDEUMR has two configurations, determined by the value of the NEW bit (see
Figure 14-15
and
Figure
14-16). The ‘old’ configuration (NEW = 0) is used by most descriptor types and is backward
compatible with previous versions of SEC 2.0. The ‘new’ configuration (NEW = 1) is only used by
descriptor type 1000_1 ‘tls_ssl_block’.
The MDEUMR is cleared when the MDEU is reset or re-initialized. Setting a reserved mode bit will
generate a data error. If the mode register is modified during processing, a context error is generated.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
14-28
Freescale Semiconductor