MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 1114

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

DUART
Except for the case when there is an overrun, URBR returns the data in the order it was received from the
transmitter. Refer to the ULSR[OE] description,
ULSR2).” Figure 18-2
UTHRs.
Table 18-4
18.3.1.2
A write to these 8-bit registers causes the UART devices to transfer 5 to 8 data bits on the UART bus in
the format set up in the ULCR (line control register). In FIFO mode, data written to UTHR is placed into
the FIFO. The data written to UTHR is the data sent onto the UART bus, and the first byte written to UTHR
is the first byte onto the bus. UDSR[TXRDY] indicates when the FIFO is full. Refer to
Table
Figure 18-3
Table 18-5
18.3.1.3
UDLB is concatenated with the divisor most significant byte register (UDMB) to create the divisor used
to divide the input clock into the DUART. The output frequency of the baud generator is 16 times the baud
rate; therefore, the desired baud rate = platform clock frequency ÷ (16 × [UDMB||UDLB]). Equivalently,
18-6
Bits
Bits
0–7
0–7
18-22.
Name
Name
DATA
DATA
describes URBR.
describes the UTHR.
shows the bits in the UTHRs.
Transmitter Holding Registers (UTHR1 and UTHR2)
Divisor Most and Least Significant Byte Registers (UDMB and UDLB)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Data that is written to UTHR [Write only]
Data received from the transmitter on the UART bus [read only]
Offset: 0x0_4500, 0x0_4600
Offset: 0x0_4500, 0x0_4600
Reset
Reset
Figure 18-3. Transmitter Holding Registers (UTHR1 and UTHR2)
shows the receiver buffer registers. Note that these registers have same offset as the
Figure 18-2. Receiver Buffer Registers (URBR1 and URBR2)
W
W
R
R
0
0
Table 18-4. URBR Field Descriptions
Table 18-5. UTHR Field Descriptions
Section 18.3.1.9, “Line Status Registers (ULSR1 and
All zeros
All zeros
Description
Description
DATA
DATA
Access: User write-only
Access: User read-only
Freescale Semiconductor
7
7
Table 18-21
and