MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 209

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Chapter 5
System Configuration
5.1
This chapter describes several functions that control the local access windows, system configuration,
protection, and general utilities. These functions are discussed in the following sections:
5.2
The device provides a flexible local memory map. The local memory map refers to the 32-bit address space
seen by the processor as it accesses memory and I/O space. Internal DMA engines also see this same local
memory map. All memory accessed by the DDR SDRAM and local bus memory controllers exists in this
memory map, as do all memory-mapped configuration, control, and status registers.
The local memory map is defined by a set of nine local access windows. Each of these windows maps a
region of memory to a particular target interface, such as the DDR SDRAM controller or the PCI
controller. The DSP subsystem is not operational in the MSC7104. Note that the local access windows do
not perform any address translation. The size of each window can be configured from 4 Kbytes to
2 Gbytes. Each local access window is assigned to a specific target interface as specified in
Freescale Semiconductor
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Section 5.2, “Local Memory Map Overview and Example”
Section 5.3, “System Configuration”
Section 5.4, “Software Watchdog Timer (WDT)”
Section 5.5, “Real Time Clock Module (RTC)”
Section 5.6, “Periodic Interval Timer (PIT)”
Section 5.7, “General-Purpose Timers (GTMs)”
Section 5.8, “Power Management Control (PMC)”
Introduction
Local Memory Map Overview and Example
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Window Number
0
1
2
3
4
5
6
Table 5-1. Local Access Windows Target Interface
Configuration registers (IMMR)
Local bus
Local bus
Local bus
Local bus
PCI
PCI
Target Interface
Fixed 1-Mbyte window size
Comments
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Table
5-1.
5-1