MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 4

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MPC8313CZQADDC

Manufacturer Part Number
MPC8313CZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MPC8313CZQADDC

Processor Series
MPC8313
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MPC8313CZQADDC
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Paragraph
Number
2.1
2.2
2.3
3.1
3.2
3.3
3.4
4.1
4.1.1
4.1.2
4.2
4.2.1
4.2.1.1
4.2.1.2
4.2.2
4.2.3
4.2.4
4.3
4.3.1
4.3.1.1
4.3.1.2
4.3.1.3
4.3.2
4.3.2.1
4.3.2.1.1
4.3.2.2
4.3.2.2.1
4.3.2.2.2
4.3.2.2.3
4.3.2.2.4
iv
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Internal Memory Mapped Registers ................................................................................ 2-1
Accessing IMMR Memory From the Local Processor .................................................... 2-1
Complete IMMR Map ..................................................................................................... 2-1
Signals Overview ............................................................................................................. 3-1
Configuration Signals Sampled at Reset ....................................................................... 3-12
Output Signal States During Reset ................................................................................ 3-13
External Signal Description ........................................................................................... 3-14
External Signals ............................................................................................................... 4-1
Functional Description..................................................................................................... 4-4
Reset Configuration ......................................................................................................... 4-9
Reset Signals................................................................................................................ 4-1
Clock Signals ............................................................................................................... 4-3
Reset Operations .......................................................................................................... 4-4
Power-On Reset Flow.................................................................................................. 4-6
Hard Reset Flow .......................................................................................................... 4-8
Soft Reset Flow............................................................................................................ 4-9
Reset Configuration Signals ........................................................................................ 4-9
Reset Configuration Words........................................................................................ 4-12
Reset Causes ............................................................................................................ 4-5
Reset Actions ........................................................................................................... 4-5
Reset Configuration Word Source ......................................................................... 4-10
SYS_CLK_IN Division ......................................................................................... 4-11
Selecting Reset Configuration Input Signals ......................................................... 4-11
Reset Configuration Word Low Register (RCWLR)............................................. 4-13
Reset Configuration Word High Register (RCWHR)............................................ 4-14
System PLL Configuration................................................................................ 4-13
PCI Host/Agent Configuration .......................................................................... 4-16
Boot Memory Space (BMS) .............................................................................. 4-17
Boot Sequencer Configuration .......................................................................... 4-17
Boot ROM Location .......................................................................................... 4-18
Reset, Clocking, and Initialization
Signal Descriptions
Contents
Memory Map
Chapter 2
Chapter 3
Chapter 4
Title
Freescale Semiconductor
Number
Page

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