HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 10

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

7.7
7.8
7.9
7.10 Additional Items................................................................................................................. 346
7.11 Usage Notes ....................................................................................................................... 349
Section 8
8.1
8.2
8.3
8.4
8.5
8.6
vi
7.6.6
7.6.7
7.6.8
7.6.9
Burst ROM Interface.......................................................................................................... 335
Idles between Cycles.......................................................................................................... 339
Bus Arbitration................................................................................................................... 340
7.9.1
7.10.1 Resets.................................................................................................................... 346
7.10.2 Access as Viewed from CPU, DMAC or E-DMAC............................................. 346
7.10.3 STATS1 and STATS0 Pins .................................................................................. 348
7.10.4 BUSHiZ Specification.......................................................................................... 348
7.11.1 Normal Space Access after Synchronous DRAM Write when Using DMAC..... 349
7.11.2 When Using I : E Clock Ratio of 1 : 1, 8-Bit Bus Width,
Introduction........................................................................................................................ 353
8.1.1
Register Description........................................................................................................... 354
8.2.1
Address Space and the Cache ............................................................................................ 356
Cache Operation................................................................................................................. 357
8.4.1
8.4.2
8.4.3
8.4.4
8.4.5
8.4.6
8.4.7
8.4.8
8.4.9
8.4.10 Address Array Access........................................................................................... 366
Cache Use .......................................................................................................................... 367
8.5.1
8.5.2
8.5.3
8.5.4
Usage Notes ....................................................................................................................... 370
8.6.1
8.6.2
EDO Mode............................................................................................................ 328
DRAM Single Transfer......................................................................................... 332
Refreshing ............................................................................................................. 333
Power-On Sequence.............................................................................................. 335
Master Mode ......................................................................................................... 345
and External Wait Input........................................................................................ 351
Cache
Register Configuration.......................................................................................... 354
Cache Control Register (CCR) ............................................................................. 354
Cache Reads.......................................................................................................... 357
Write Access ......................................................................................................... 359
Cache-Through Access ......................................................................................... 362
The TAS Instruction ............................................................................................. 362
Pseudo-LRU and Cache Replacement.................................................................. 362
Cache Initialization ............................................................................................... 364
Associative Purges................................................................................................ 364
Cache Flushing...................................................................................................... 365
Data Array Access ................................................................................................ 365
Initialization.......................................................................................................... 367
Purge of Specific Lines......................................................................................... 368
Cache Data Coherency.......................................................................................... 368
Two-Way Cache Mode ......................................................................................... 369
Standby ................................................................................................................. 370
Cache Control Register ......................................................................................... 370
.................................................................................................................. 353