HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 436

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

Bit 24: RFCOF
0
1
Note: The receive FIFO in the E-DMAC can hold up to eight frames. If a ninth frame is received
Bit 23—Reserved: These bits should only be written with 0.
Bit 22—EtherC States Register Interrupt (ECI): Indicates that an interrupt due to an EtherC status
register (ECSR) source has been detected.
Bit 22: ECI
0
1
Note: EESR is a read-only register. When this register is cleared by a source in ECSR in the
Bit 21—Tx Complete (TC): Indicates that all the data specified by the transmit descriptor has been
transmitted to the EtherC. The transfer status is written back to the relevant descriptor. When 1-
frame transmission is completed for 1-frame/1-buffer processing, or when the last data in the
frame is transmitted and the transmission descriptor valid bit (TACT) in the next descriptor is not
set for multiple-frame buffer processing, transmission is completed and this bit is set to 1. After
frame transmission, the E-DMAC writes the transmission status back to the descriptor.
Bit 21: TC
0
1
Note: As data is sent onto the line by the PHY-LSI from the EtherC via the MII, the actual
Bit 20—Tx Descriptor Exhausted (TDE): Indicates that the transmission descriptor valid bit
(TACT) in the descriptor is not set when the E-DMAC reads the transmission descriptor when the
previous descriptor is not the last one of the frame for multiple- buffer frame processing. As a
result, an incomplete frame may be transmitted.
when there are already eight frames in the receive FIFO, the receive frame counter
overflows and the ninth frame is discarded. Discarded frames are counted by the missed-
frame counter register. The eight frames in the receive FIFO are retained, and are
transferred to memory when DMA transfer becomes possible. When the frame counter
value falls below 8, another frame is received.
EtherC, this bit is also cleared.
transmission completion time is longer.
Description
Receive frame counter has not overflowed
Receive frame counter overflow (interrupt source)
Description
EtherC status interrupt source not detected
EtherC status interrupt source detected (interrupt source)
Description
Transfer not complete, or no transfer directive
Transfer complete (interrupt source)
(Initial value)
(Initial value)
(Initial value)
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