HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 779

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HD6417615

Manufacturer Part Number
HD6417615
Description
Hardware Manual
Manufacturer
Hitachi Semiconductor
Datasheet

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6. When PLL circuit 1 is operational, the WDT starts counting up inside the chip. When PLL
7. When the internal clock stabilizes, the CKPACK pin goes high, giving external notification
The standby state, all on-chip peripheral module states, and all pin states during clock pause are
the same as in the normal standby mode. Figure 20.2 shows the timing chart for the clock pause
function.
CKPREQ/CKM
circuit 1 is halted, the WDT is not activated.
that the chip can be operated.
CKIO input
CKPACK
Figure 20.2 Clock Pause Function Timing Chart (PLL Circuit 1 Operating)
output
input
Clock pause
acceptance
processing
Frequency
modification
Clock pause state
Clock pause request
cancellation
WDT count-up
Normal state
769

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