HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 317

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

7.5.6
Burst write mode can be selected by setting the BWE bit to 1 in BCR3. The basic timing charts for
burst write access is shown in figure 7.23 (a) and (b). This example assumes a 32-bit bus width
and a burst length of 4. In the burst write cycle, the WRITA command that performs auto-
precharge is issued in Tc1 following the ACTV command Tr cycle. The first 4 bytes of write data
are output simultaneously with the WRITA command in Tc, and the remaining 12 bytes of data
are output consecutively in Tc2, Tc3, and Tc4. In a write with auto-precharge, as with a single
write, a Trw1 cycle that provides the waiting time until precharge is started is inserted after output
of the write data, followed by a Tap cycle for the precharge wait in a write access. The Trw1 and
Tap cycles can be set respectively in MCR by bits TRWL1 and TRWL0, and bits TRP1 and
TRP0.
300
Burst Write Mode
CKIO
A24–A11
A10
A9–A1
CS2 or CS3
RAS
CAS
RD/WR
DQMxx
D31–D0
DACKn*
Note: * DACKn waveform when active-low is specified.
Figure 7.22 Basic Single Write Cycle Timing (Auto-Precharge)
Tr
Tc
Trwl
Tap