HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 304

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HD6417615

Manufacturer Part Number
HD6417615
Description
Hardware Manual
Manufacturer
Hitachi Semiconductor
Datasheet

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7.4.3
Idle cycles can be inserted to prevent extension of the RD or WEn assertion period beyond the
length of the CSn assertion period by setting control bits in WCR3. This allows for flexible
interfacing to external circuit. The timing is shown in figure 7.16. Th and Tf cycles are added
respectively before and after the ordinary cycle. Signals other than RD and WEn are asserted in
this cycle, but RD and WEn are not. In addition, data is extended up to the Tf cycle, which is
effective for devices with slow write operations.
Read
Write
Note: * DACKn waveform when active-low is specified.
CS Assertion Period Extension
RD/WR
DACKn*
CKIO
Address
CSn
BS
RD
Data
WEn
Data
Figure 7.16 CS Assertion Period Extension Function
Th
T1
T2
Tf
287

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