HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 270

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

Table 7.1
Signal
DREQ1
DACK1
REFOUT
DQMUU/
WE3
DQMUL/
WE2
DQMLU/
WE1
DQMLL/
WE0
CAS3
CAS2
CAS1
CAS0
STATS0, 1 O
BUSHIZ
Note: Hi-Z: High impedance
I/O
I
O
O
O
O
O
O
O
O
O
O
I
Pin Configuration (cont)
With Bus
Released
I
O
O
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
O
I
Description
DMA request 1
DMA acknowledge 1
Refresh execution request output when bus is released
When synchronous DRAM is used, connected to DQM pin for the
most significant byte (D31–D24). For ordinary space, indicates
writing to the most significant byte
When synchronous DRAM is used, connected to DQM pin for the
D23–D16. For ordinary space, indicates writing to the second byte
When synchronous DRAM is used, connected to DQM pin for the
D15–D8. For ordinary space, indicates writing to the third byte
When synchronous DRAM is used, connected to DQM pin for the
least significant byte (D7–D0). For ordinary space, indicates writing
to the least significant byte
When DRAM is used, connected to CAS pin for the most significant
byte (D31–D24)
When DRAM is used, connected to CAS pin for the second byte
(D23–D16)
When DRAM is used, connected to CAS pin for the third byte (D15–
D8)
When DRAM is used, connected to CAS pin for the least significant
byte (D7–D0)
Bus master identification 00: CPU
Signal used in combination with WAIT signal to place bus and
strobe signals in the high-impedance state without the ending bus
cycle.
01: DMAC
10: E-DMAC
11: Other
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