HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 261

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

D. Register settings: BBRA = H'0000
As the channel C break condition is a write cycle, the condition is not matched, and as the
sequential conditions are not satisfied, a user break interrupt is not generated.
After the instruction at address H'0000500 is executed, and the instruction at address
H'00000A00 is executed five times, a user break interrupt is generated after the instruction at
address H'00001000 has been executed nine times, but before it is executed a tenth time.
Channel C: Address:
Channel D: Address:
BARB = H'00000500 / BAMRB = H'00000000 / BBRB = H'0057
BARC = H'00000A00 / BAMRC = H'00000000 / BBRC = H'0057
BDRC = H'00000000 / BDMRC = H'00000000
BARD = H'00001000 / BAMRD = H'00000000 / BBRD = H'0057
BDRD = H'00000000 / BDMRD = H'00000000
BRCR = H'00102020 / BETRC = H'0005 / BETRD = H'000A
Channel A: Not used
Channel B: Address:
Channel C: Address:
Channel D: Address: H'00001000; address mask: H'00000000
Data:
Bus cycle: CPU, instruction fetch (pre-execution), write, word
Data:
Bus cycle: CPU, instruction fetch (pre-execution), read, word
Data:
Bus cycle: CPU, instruction fetch (pre-execution), read, word
Data:
Bus cycle: CPU, instruction fetch (pre-execution), read, word
Execution-times break enabled (5 times)
Data:
Bus cycle: CPU, instruction fetch (pre-execution), read, word
Execution-times break enabled (10 times)
H'00037226; address mask: H'00000000
H'00000000; data mask: H'00000000
H'0003722E; address mask: H'00000000
H'00000000; data mask: H'00000000
H'00000500; address mask: H'00000000
H'00000000; data mask: H'00000000
H'00000A00; address mask: H'00000000
H'00000000; data mask: H'00000000
H'00000000; data mask: H'00000000
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