HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 664

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

Bit 4—Buffer Operation A (BFA): Specifies whether TGRA is to operate in the normal way, or
TGRA and TGRC are to be used together for buffer operation. When TGRC is used as a buffer
register, TGRC input capture/output compare is not generated.
In channels 1, and 2, which have no TGRC, bit 4 is reserved. It is always read as 0 and cannot be
modified.
Bit 4: BFA
0
1
Bits 3 to 0—Modes 3 to 0 (MD3 to MD0): These bits are used to set the timer operating mode.
Bit 3:
MD3*
0
1
Notes: 1. MD3 is a reserved bit. In a write, it should always be written with 0.
652
1
2. Phase counting mode cannot be set for channel 0. In this case, 0 should always be
Bit 2:
MD2*
0
1
*
written to MD2.
2
Description
TGRA operates normally
TGRA and TGRC used together for buffer operation
Bit 1:
MD1
0
1
0
1
*
Bit 0:
MD0
0
1
0
1
0
1
0
1
*
Description
Normal operation
Reserved
PWM mode 1
PWM mode 2
Phase counting mode 1
Phase counting mode 2
Phase counting mode 3
Phase counting mode 4
—
(Initial value)
(Initial value)
*: Don’t care