HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 358

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

However, only one E-DMAC channel can hold the bus during one bus-mastership cycle.
The E-DMAC has two channels to handle both transmission and reception. Arbitration between
the channels is performed automatically within the E-DMAC module, with bus mastership
alternating between the transmit channel and the receive channel. For arbitration between the two
DMAC channels, either fixed priority mode or round robin mode can be selected by means of the
priority mode bit (PR) in the DMA operation register (DMAOR).
When the bus is being passed between slave and master, all bus control signals are negated before
the bus is released to prevent erroneous operation of the connected devices. When the bus is
transferred, also, the bus control signals begin bus driving from the negated state. The master and
slave passing the bus between them drive the same signal values, so output buffer conflict is
avoided. A pull-up resistance is required for the bus control signals to prevent malfunction caused
by external noise when they are at high impedance.
Bus permission is granted at the end of the bus cycle. When the bus is requested, the bus is
released immediately if there is no ongoing bus cycle. If there is a current bus cycle, the bus is not
released until the bus cycle ends. Even when a bus cycle does not appear to be in progress when
viewed from off-chip, it is not possible to determine immediately whether the bus has been
released by looking at CSn or other control signals, since a bus cycle (such as wait insertion
between access cycles) may have been started internally. The bus cannot be released during burst
transfers for cache filling, DMAC 16-byte block transfers (16 + 16 = 32-byte transfers in dual
address mode), or E-DMAC 16-byte block transfers. Likewise, the bus cannot be released between
the read and write cycles of a TAS instruction. Arbitration is also not performed between multiple
bus cycles produced by a data width smaller than the access size, such as a longword access to an
8-bit data width memory. Bus arbitration is performed between external vector fetch, PC save, and
SR save cycles during interrupt handling, which are all independent accesses.
Because the CPU is connected to cache memory by a dedicated internal bus, cache memory can be
read even when the bus is being used by another bus master on the chip or externally. When
writing from the CPU, an external write cycle is produced. Since the internal bus that connects the
CPU, DMAC, and on-chip peripheral modules can operate in parallel to the external bus, both read
and write accesses from the CPU to on-chip peripheral modules and from the DMAC to on-chip
peripheral modules are possible even if the external bus is not held.
Figures 7.54 (a) and 7.54 (b) show the timing charts in the cases that bus requests occur
simultaneously from the E-DMAC, DMAC, and CPU. These cases are based on the following
settings:
The CS2 and CS3 spaces are set for synchronous DRAM.
The CAS latency is one cycle.
Refresh request
External device
E-DMAC
DMAC
CPU
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