HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 665

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

16.2.3
Channel 0: TIOR0H
Channel 1: TIOR1
Channel 2: TIOR2
Channel 0: TIOR0L
Note: When TGRC or TGRD is designated for buffer operation, this setting is invalid and the
The TIOR registers are 8-bit registers that control the TGR registers. The TPU has four TIOR
registers, two for channel 0 and one each for channels 1, and 2. The TIOR registers are initialized
to H'00 by a reset.
Note that TIOR is affected by the TMDR setting.
The initial output specified by TIOR becomes valid when the counter is halted (i.e. when the CST
bit is cleared to 0 in TSTR). In PWM mode 2, the output at the point at which the counter is
cleared to 0 is specified.
Initial value:
Initial value:
register operates as a buffer register.
Timer I/O Control Register (TIOR)
R/W:
R/W:
Bit:
Bit:
IOB3
IOD3
R/W
R/W
7
0
7
0
IOB2
IOD2
R/W
R/W
6
0
6
0
IOB1
IOD1
R/W
R/W
5
0
5
0
IOB0
IOD0
R/W
R/W
4
0
4
0
IOA3
IOC3
R/W
R/W
3
0
3
0
IOA2
IOC2
R/W
R/W
2
0
2
0
IOA1
IOC1
R/W
R/W
1
0
1
0
IOA0
IOC0
R/W
R/W
0
0
0
0
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