HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 384

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

8.5.2
There is no snoop function (for monitoring data rewrites), so specific lines of cache must be
purged when the contents of cache memory and external memory differ as a result of an operation.
For instance, when a DMA transfer is performed to the cache area, cache lines corresponding to
the rewritten address area must be purged. All entries of the cache can be purged by setting the CP
bit in CCR to 1. However, it is efficient to purge only specific lines if only a limited number of
entries are to be purged.
An associative purge is used to purge specific lines. Since cache lines are 16 bytes long, purges are
performed in a 16-byte units. The four ways are checked simultaneously, and only lines holding
data corresponding to specified addresses are purged. When addresses do not match, the data at
the specified address is not fetched to the cache, so no purge occurs.
;
MOV.L
XOR
MOV.L
ADD
MOV.L
When it is troublesome to purge the cache after every DMA transfer, it is recommended that the
OD bit in CCR be set to 1 in advance. When the OD bit is 1, the cache operates as cache memory
only for instructions. However, when data is already fetched into cache memory, specific lines of
cache memory must be purged for DMA transfers.
8.5.3
The cache memory does not have a snoop function. This means that when data is shared with a
bus master other than the CPU, software must be used to ensure the coherency of data. For this
purpose, the cache-through area can be used, or a cache purge can be performed with program
logic using write-through.
When the cache-through area is to be used, the data shared by the bus masters is placed in the
cache-through area. This makes it easy to maintain data coherency, since access of the cache-
through area does not fetch data into the cache. When the shared data is accessed repeatedly and
the frequency of data rewrites is low, a lower access speed can adversely affect performance.
To purge the cache using program logic, the data updates are detected by the program flow and the
cache is then purged. For example, if the program inputs data from a disk, whenever reading of a
unit (such as a sector) is completed, the buffer address used for reading or the entire cache is
368
Purging 32 bytes from address R3
Purge of Specific Lines
Cache Data Coherency
#H'40000000, R0
R1, R1
R1, @(R0, R3)
#16, R3
R1, @(R0, R3)
Figure 8.15 Purging Specific Addresses