HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 521

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

11.3.9
Purpose of New Specifications for BH: When the SH7615 is connected to the PCI bus as an
external bus, Grew logic must be used externally because the SH7615 is not equipped with a PCI
bus interface.
The PCI bus uses burst transfer principally, and performance is poor if data is transferred in small
increments.
Due to these properties of the PCI bus, it is necessary to use Grew logic externally to compare the
present address and the next address and determine whether burst transfer is possible. However,
the size of the external Grew logic increases if address comparisons are required, and there is also
the possibility that delays may interfere with timing requirements.
The specifications for BH have therefore been updated in order to solve these problems. Now if
burst transfer is possible using the present address this information is passed to the external Grew
logic. This provides enhanced support for PCI bus connections.
Register Settings When Using BH Pin: BH is output from only when the 16-byte transfer mode
is selected using the DMAC built into the SH7615. However, it is not output when SDRAM or
DRAM are accessed. When using the 16-byte transfer mode, specify auto-request mode or the
external request mode with edge detection. If external request mode with level detection or on-
chip module request mode is specified, operation is not guaranteed.
To use BH, the settings for the CHCR0 register or CHCR1 register in the on-chip DMAC of the
SH7615 must be as shown in figure 11.43. BH is not output unless the settings for the CHCR0
register or CHCR1 register are as indicated in figure 11.42.
506
Bit name
Bit name
Setting
Setting
Bit
Bit
DM1
BH Pin Output Timing
31
15
—
0
0
DM0
30
14
—
0
1
SM1
29
13
—
0
0
SM0
Figure 11.42 Register Settings When Using BH
28
12
—
0
1
TS1
27
11
—
0
1
TS0
26
—
10
0
1
16-byte unit (four long words transferred)
Source address is incremented
Destination address is incremented
AR
25
—
0
9
*
AM
24
—
0
8
*
AL
23
—
0
7
*
DS
22
—
0
6
*
DL
21
—
0
5
*
TB
20
—
0
4
*
TA
19
—
0
3
*
18
—
IE
0
2
*
* Don't care
TE
17
—
0
1
*
DE
16
—
0
0
1
DMA transfer
allowed