HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 53

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

Table 2.1
Bit
27–16
11
10
9
8
7–4
3–2
1
0
31–28
15–12
SR Register Bits
Name (Abbreviation)
Repeat counter (RC)
Y pointer usage modulo
addressing designation
(DMY)
X pointer usage modulo
addressing designation
(DMX)
M bit
Q bit
Interrupt request mask
(I3–I0)
Repeat flags (RF1, RF0)
Saturation arithmetic bit
(S)
T bit
0 bit
Function
Designate the repeat count (2–4095) for repeat (loop)
control
1: modulo addressing mode becomes valid for Y
memory address pointer, Ay (R6, R7)
1: modulo addressing mode becomes valid for X
memory address pointer, Ax (R4, R5)
Used by the DIV0S/U, DIV1 instructions
Used by the DIV0S/U, DIV1 instructions
Indicate the receive level of an interrupt request (0 to
15)
Used in zero overhead repeat (loop) control. Set as
below for an SETRC instruction
For 1 step repeat 00 RE—RS=–4
For 2 step repeat 01 RE—RS=–2
For 3 step repeat 11 RE—RS=0
For 4 steps or more 10 RE—RS>0
Used with MAC instructions and DSP instructions
1: Designates saturation arithmetic (prevents
overflows)
For MOVT, CMP/cond, TAS, TST, BT, BT/S, BF,
BF/S, SETT, CLRT and DT instructions,
0: represents false
1: represents true
For ADDV/ADDC, SUBV/SUBC, DIV0U/DIV0S, DIV1,
NEGC, SHAR/SHAL, SHLR/SHLL, ROTR/ROTL and
ROTCR/ROTCL instructions,
1: represents occurrence of carry, borrow, overflow or
underflow
0: 0 is always read out; write a 0
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