HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 467

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

occurs in the first descriptor part where the RACT bit = 1 in the figure, reception is halted
immediately and a status write-back to the descriptor is performed.
If error interrupts are enabled in the EtherC/E-DMAC status interrupt permission register
(EESIPR), an interrupt is generated immediately after the write-back. If there is a new frame
receive request, reception is continued from the buffer after that in which the error occurred.
452
E-DMAC
Inactivates RACT and writes RFE, RFS
Descriptor read
Figure 10.7 E-DMAC Operation after Receive Error
:
:
:
:
:
Write-back
0 0
0 0
0 0
0 0
1 0
1 0
1 0
1 0
1 1
Descriptors
1 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
Buffer
Start of frame
New frame reception
continues from this buffer
Receive error occurrence
Received data
Unreceived data