HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 457

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

Tx Descriptor 0 (TD0): TD0 indicates the transmit frame status. The CPU and E-DMAC use
TD0 to report the frame transmission status.
Bit 31—Tx Descriptor Active (TACT): Indicates that this descriptor is active. The CPU sets this
bit after transmit data has been transferred to the transmit buffer. The E-DMAC resets this bit on
completion of a frame transfer or when transmission is suspended.
Bit 31: TACT
0
1
Bit 30—Tx Descriptor List Last (TDLE): Indicates that this descriptor is the last in the transmit
descriptor list. After completion of the corresponding buffer transfer, the E-DMAC references the
first descriptor. This specification is used to set a ring configuration for the transmit descriptors.
Bit 30: TDLE
0
1
Bits 29 and 28—Tx Frame Position 1, 0 (TFP1, TFP0): These two bits specify the relationship
between the transmit buffer and transmit frame.
442
Description
The transmit descriptor is invalid
Indicates that valid data has not been written to the transmit buffer by the CPU,
or this bit has been reset by a write-back operation on termination of E-DMAC
frame transfer processing (completion or suspension of transmission)
If this state is recognized in an E-DMAC descriptor read, the E-DMAC
terminates transmit processing and transmit operations cannot be continued (a
restart is necessary)
The transmit descriptor is valid
Indicates that valid data has been written to the transmit buffer by the CPU and
frame transfer processing has not yet been executed, or that frame transfer is
in progress
When this state is recognized in an E-DMAC descriptor read, the E-DMAC
continues with the transmit operation
Description
This is not the last transmit descriptor list
This is the last transmit descriptor list