HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 554

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HD6417615

Manufacturer Part Number
HD6417615
Description
Hardware Manual
Manufacturer
Hitachi Semiconductor
Datasheet

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13.3
13.3.1
To use the WDT as a watchdog timer, set the WT/IT and TME bits in WTCSR to 1. Software
must prevent WTCNT overflow by rewriting the WTCNT value (normally by writing H'00) before
overflow occurs. Thus, WTCNT will not overflow while the system is operating normally, but if
WTCNT fails to be rewritten and overflows occur due to a system crash or the like, a WDTOVF
signal is output (figure 13.4). The WDTOVF signal can be used to reset the system. The
WDTOVF signal is output for 512 clock cycles.
If the RSTE bit in RSTCSR is set to 1, a signal to reset the chip will be generated internally
simultaneously with the WDTOVF signal when WTCNT overflows. Either a power-on reset or a
manual reset can be selected by the RSTS bit. The internal reset signal is output for 2048 clock
cycles.
If a reset due to the input signal from the RES pin and a reset due to WDT overflow occur
simultaneously, the RES reset takes priority and the WOVF bit in RSTCSR is cleared to 0.
540
Operation
Operation in Watchdog Timer Mode

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