HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 307

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

7.5.2
Addresses are multiplexed according to the MCR’s address multiplex specification bits AMX2–
AMX0 and size specification bit SZ so that synchronous DRAMs can be connected to the SH7615
directly without an external multiplex circuit Table 7.6 shows the relationship between the
multiplex specification bits and bit output to the address pins.
A24–A16 always output the original value regardless of multiplexing.
When SZ = 0, the data width on the synchronous DRAM side is 16 bits and the LSB of the
device’s address pins (A0) specifies word address. The A0 pin of the synchronous DRAM is thus
connected to the A1 pin of the SH7615, the rest of the connection proceeding in the same order,
beginning with the A1 pin to the A2 pin.
When SZ = 1, the data width on the synchronous DRAM side is 32 bits and the LSB of the
device’s address pins (A0) specifies longword address. The A0 pin of the synchronous DRAM is
thus connected to the A2 pin of the SH7615, the rest of the connection proceeding in the same
order, beginning with the A1 pin to the A3 pin.
290
Address Multiplexing
DQMLU/WE1
Figure 7.18 Synchronous DRAM 16-bit Device Connection
Chip
DQMLL/WE0
CAS/OE
RD/WR
CKIO
CKE
RAS
CSn
D15
A10
D0
A1
256 k
A9
A0
CLK
CKE
CS
RAS
CAS
WE
I/O15
I/O0
DQMU
DQML
synchronous
DRAM
16-bit