HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 590

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

14.2.11 FIFO Data Count Register (SCFDR)
The FIFO data count register (SCFDR) is a 16-bit register that indicates the number of data bytes
stored in the transmit FIFO data register (SCFTDR) and receive FIFO data register (SCFRDR).
The upper 8 bits show the number of transmit data bytes in SCFTDR, and the lower 8 bits show
the number of receive data bytes in SCFRDR.
SCFDR can be read by the CPU at all times.
SCFDR is initialized to H'00 by a reset, by the module standby function, and in standby mode. It is
also initialized to H'00 by setting the TFRST and RFRST bits to 1 in SCFCR to reset SCFTDR
and SCFRDR to the empty state.
Bits 15 to 13—Reserved: These bits are always read as 0. The write value should always be 0.
Bits 12 to 8—Transmit FIFO Data Count 4 to 0 (T4 to T0): These bits show the number of
untransmitted data bytes in SCFTDR.
A value of H'00 indicates that there is no transmit data, and a value of H'10 indicates that
SCFTDR is full of transmit data. The value is cleared to H'00 by transmitting all the data, as well
as by the above initialization conditions.
Bits 7 to 5—Reserved: These bits are always read as 0. The write value should always be 0.
Bits 4 to 0—Receive FIFO Data Count 4 to 0 (R4 to R0): These bits show the number of receive
data bytes in SCFRDR.
A value of H'00 indicates that there is no receive data, and a value of H'10 indicates that SCFRDR
is full of receive data. The value is cleared to H'00 by reading all the receive data from SCFRDR,
as well as by the above initialization conditions.
Upper 8 bits:
Lower 8 bits:
Initial value:
Initial value:
R/W:
R/W:
15
—
—
0
R
7
0
R
14
—
—
0
R
6
0
R
13
—
—
0
R
5
0
R
T4
R4
12
0
R
4
0
R
T3
R3
11
0
R
3
0
R
T2
R2
10
0
R
2
0
R
T1
R1
9
0
R
1
0
R
T0
R0
8
0
R
0
0
R
577