HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 357

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

7.9
The chip has a bus arbitration function that, when a bus release request is received from an
external device, releases the bus to that device after the bus cycle being executed is completed.
The chip keeps the bus under normal conditions and permits other devices to use the bus by
releasing it when they request its use.
In the following explanation, external devices requesting the bus are called slaves.
The chip has three internal bus masters, the CPU, the DMAC and the E-DMAC. When
synchronous DRAM or DRAM is connected and refresh control is performed, the refresh request
becomes a third master. In addition to these, there are also bus requests from external devices. The
priority for bus requests when they occur simultaneously is as follows.
340
CKIO
A24–A0
CSm
CSn
BS
RD/WR
RD
D31–D0
Bus Arbitration
CSm space read
T1
(reading different spaces)
between CSm accesses
Specification of waits
T2
Figure 7.53 Idles between Cycles
Twait
CSn space read
T1
T2
between CSn accesses
(read followed by write)
Specification of waits
Twait
CSn space write
T1
T2