HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 168

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

5.2.6
On-chip peripheral module interrupts are interrupts generated by the following 9 on-chip
peripheral modules:
A different interrupt vector is assigned to each interrupt source, so the exception service routine
does not have to decide which interrupt has occurred. Priority levels between 0 and 15 can be
assigned to individual on-chip peripheral modules in interrupt priority registers A–E (IPRA–
IPRE). On-chip peripheral module interrupt exception handling sets the interrupt mask level bits
(I3–I0) in the status register (SR) to the priority level value of the on-chip peripheral module
interrupt that was accepted.
5.2.7
Table 5.4 lists interrupt sources and their vector numbers, vector table address offsets and interrupt
priorities.
Each interrupt source is allocated a different vector number and vector table address offset. Vector
table addresses are calculated from vector numbers and vector table address offsets. In interrupt
exception handling, the exception service routine start address is fetched from the vector table
entry indicated by the vector table address. See table 4.4, Calculating Exception Vector Table
Addresses, in section 4, Exception Handling, for more information on this calculation.
IRL interrupts IRL15–IRL1 have interrupt priority levels of 15–1, respectively. IRQ interrupt and
on-chip peripheral module interrupt priorities can be set freely between 0 and 15 for each module
by setting interrupt priority registers A–E (IPRA–IPRE). The ranking of interrupt sources for
IPRA–IPRE, however, must be the order listed under Priority within IPR Setting Unit in table 5.4
and cannot be changed. A reset assigns priority level 0 to on-chip peripheral module interrupts. If
the same priority level is assigned to two or more interrupt sources and interrupts from those
sources occur simultaneously, their priority order is the default priority order indicated at the right
in table 5.4.
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Direct memory access controller (DMAC)
Bus state controller (BSC)
Watchdog timer (WDT)
Free-running timer (FRT)
Ethernet controller direct memory access controller (E-DMAC) (Including EtherC interrupt)
16-bit timer pulse unit (TPU)
Serial communication interface with FIFO (SCIF)
Serial I/O (SIO)
On-chip Peripheral Module Interrupts
Interrupt Exception Vectors and Priority Order