HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 215

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

6.1
The user break controller (UBC) provides functions that simplify program debugging. When break
conditions are set in the UBC, a user break interrupt is generated according to the conditions of the
bus cycle generated by the CPU or on-chip DMAC (DMAC or E-DMAC).
This function makes it easy to design a sophisticated self-monitoring debugger, enabling programs
to be debugged with the chip alone, without using an in-circuit emulator.
6.1.1
The UBC has the following features:
The following can be set as break conditions:
1. Address: 32-bit masking capability, individual address setting possible (cache bus (CPU),
2. Data (channels C and D only,): 32-bit masking capability, individual address setting
3. Bus master: CPU cycle/on-chip DMAC (DMAC, E-DMAC) cycle
4. Bus cycle: Instruction fetch/data access
5. Read/write
6. Operand cycle: Byte/word/longword
User break interrupt generation on occurrence of break condition
A user-written user break interrupt exception routine can be executed.
Processing can be stopped before or after instruction execution in an instruction fetch cycle.
Break with specification of number of executions (channels C and D only)
Settable number of executions: maximum 2
PC trace function
The branch source/branch destination can be traced when a branch instruction is fetched
(maximum 8 addresses (4 pairs)).
Number of break channels: Four (channels A, B, C, and D)
Sequential break settings
User break interrupts can be generated on independent or sequential conditions for
channels A, B, C, and D.
internal bus (DMAC, E-DMAC), X/Y bus)
possible (cache bus (CPU), internal bus (DMAC, E-DMAC), X/Y bus)
Overview
Features
Channel A
Channel B
Channel C
Section 6 User Break Controller (UBC)
channel C
channel D
channel B
channel D
channel C
12
– 1 (4095)
channel D
197