HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 335

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

command, and eight idle cycles between auto-refresh commands, and between the eighth auto-
refresh command and the mode register write command, regardless of the MCR setting.
After writing to the synchronous DRAM mode register, perform a dummy read to each
synchronous DRAM bank before starting normal access. This will initialize the SH7615's internal
address comparator.
Synchronous DRAM requires a fixed idle time after powering on before the all-bank precharge
command is issued. Refer to the synchronous DRAM manual for the necessary idle time. When
the pulse width of the reset signal is longer than the idle time, the mode register may be set
immediately without problem. However, care is required if the pulse width of the reset signal is
shorter than the idle time.
318
CKIO
A24–A11
A10
A9–A1
CS2 or CS3
RAS
CAS
RD/WR
DQMxx
PALL
Tp
Tpw
Figure 7.33 Synchronous DRAM Mode Write Timing
Tpw
Tpw
REF
Trr
Trc
Trc
REF
Trr
Trc
Trc
Tmw
MRS