HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 579

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

Bit 3—Multiprocessor bit (MPB): When reception is performed using a multiprocessor format in
asynchronous mode, MPB stores the multiprocessor bit in the receive data.
The MPB flag is read-only and cannot be modified.
Bit 3: MPB
0
1
Note: * Retains its previous state when the RE bit is cleared to 0 while using a multiprocessor
Bit 2—Multiprocessor Bit Transfer (MPBT): When transmission is performed using a
multiprocessor format in asynchronous mode, MPBT stores the multiprocessor bit to be added to
the transmit data.
The MPBT bit setting is invalid in synchronous mode and IrDA mode, when a multiprocessor
format is not used, and when the operation is not transmission.
Bit 2: MPBT
0
1
Bit 1—Receive Data Error Ignore Enable (EI): Selects whether or not the receive operation is to
be continued when a framing error or parity error occurs in receive data (ER = 1).
Bit 1: EI
0
1
Note: When EI = 0, only the last data in SCFRDR is treated as data containing an error. When EI
566
format.
= 1, receive data is sent to SCFRDR even if it contains an error.
Description
Data with a 0 multiprocessor bit has been received*
Data with a 1 multiprocessor bit has been received
Description
Data with a 0 multiprocessor bit is transmitted
Data with a 1 multiprocessor bit is transmitted
Description
Receive operation is halted when framing error or parity error occurs during
reception (ER = 1)
Receive operation is continued when framing error or parity error occurs during
reception (ER = 1)
(Initial value)
(Initial value)
(Initial value)