HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 74

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

2.4.2
There are two different kinds of memory accesses with DSP instructions. One type is with the X,
Y data transfer instructions (MOVX.W, MOVY.W), and the other is with the single data transfer
instructions (MOVS.W, MOVS.L). The data addressing differs between these two types of
instructions. Table 2.13 shows a summary of the data transfer instructions.
Table 2.13 Overview of Data Transfer Instructions
Classification
Address registers
Index registers
Addressing
Modulo addressing
Data bus
Data length
Bus contention
Memory
Source registers
Destination registers
X, Y Data Addressing: Among the DSP instructions, the MOVX.W and MOVY.W instructions
can be used to simultaneously access X, Y data memory. The DSP instructions have two address
pointers for simultaneous accessing of X, Y data memory. Only pointer addressing is possible with
DSP instructions; there is no immediate addressing. The address registers are divided into two; the
R4, R5 registers become the X memory address register (Ax), and the R6, R7 registers become the
Y memory address register (Ay). The following three types of addressing exist with X, Y data
transfer instructions.
1. Non-updated address registers: The Ax, Ay registers are address pointers. They are not
2. Add index registers: The Ax, Ay registers are address pointers. The Ix, Iy register values are
3. Increment address registers: The Ax, Ay registers are address pointers. The value +2 is added
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updated.
added to them, respectively, after the data transfer (post-update).
to each of them after the data transfer (post-update).
DSP Data Addressing
X, Y Data Transfer Processing
(MOVX.W, MOVY.W)
Ax: R4, R5; Ay: R6, R7
Ix: R8, Iy: R9
Nop/Inc(+2)/index addition: post-
update
—
Possible
XDB, YDB
16 bit (word)
None
X, Y data memory
Dx, Dy: A0, A1
Dx: X0/X1; Dy: Y0/Y1
Single Data Transfer Processing
(MOVS.W, MOVS.L)
As: R2, R3, R4, R5
Is: R8
Nop/Inc(+2,+4)/index addition: post-
update
Dec(–2,–4): pre-update
Not possible
CDB
16 bit/32 bit (word/longword)
Yes
All memory spaces
Ds: A0/A1, M0/M1, X0/X1, Y0/Y1,
A0G, A1G
Ds: A0/A1, M0/M1, X0/X1, Y0/Y1,
A0G, A1G