HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 480

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

11.2.6
DMA request/response selection control registers 0 and 1 (DRCR0, DRCR1) are 8-bit read/write
registers that set the DMAC transfer request source. They are written as 8-bit values. They are
initialized to H'00 by a reset, but retain their values in standby mode and a module standby.
Bits 7 to 5—Reserved: These bits are always read as 0. The write value should always be 0.
Bits 4 to 0—Resource Select Bits 4 to 0 (RS4–RS0): Specify which transfer request to input to the
DMAC. Changing the transfer request source must be done when the DMA enable bit (DE) is 0.
See section 11.3.4, DMA Transfer Types, for the possible setting combinations.
Bit 4:
RS4
0
Initial value:
Bit 3:
RS3
0
1
DMA Request/Response Selection Control Registers 0 and 1 (DRCR0, DRCR1)
R/W:
Bit:
Bit 2:
RS2
0
1
1
0
1
—
7
0
R
Bit 1:
RS1
0
1
0
1
1
0
1
0
—
6
0
R
Bit 0:
RS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
—
5
0
R
Description
DREQ (external request)
Reserved (setting prohibited)
Reserved (setting prohibited)
Reserved (setting prohibited)
Reserved (setting prohibited)
SCIF channel 1 RXI (on-chip SCI with FIFO channel
1 receive-data-full interrupt request)*
SCIF channel 1 TXI (on-chip SCI with FIFO channel
1 transmit-data-empty interrupt request)*
Reserved (setting prohibited)
Reserved (setting prohibited)
SCIF channel 2 RXI (on-chip SCI with FIFO channel
2 receive-data-full interrupt request)*
SCIF channel 2 TXI (on-chip SCI with FIFO channel
2 transmit-data-empty interrupt request)*
Reserved (setting prohibited)
TPU TGI0A (on-chip TPU input capture channel 0A
interrupt request)*
TPU TGI0B (on-chip TPU input capture channel 0B
interrupt request)*
RS4
R/W
4
0
RS3
R/W
3
0
RS2
R/W
2
0
RS1
R/W
1
0
(Initial value)
RS0
R/W
0
0
465