HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 282

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

7.2.5
Bits 15 and 14—Number of External Waits Specification for Area 4 (A4WD1, A4WD0): These
bits specify the number of cycles between acceptance of CS4 space external wait negation and RD
or WEn negation.
Bit 15: A4WD1
0
1
Bit 13—Reserved bit. This bit is always read as 0. The write value should always be 0.
Bits 12 to 8—External Wait Mask Specification for Areas 0 to 4 (A4WM–A0WM): These bits
enable waits to be masked for CS spaces 0 to 4. When a value other than 00 is set in the wait
control bits for CS spaces 0 to 4 (W41–W00), external wait input can be enabled, but the wait
input can be masked by setting these bits to 1. With synchronous DRAM, external wait input is
ignored regardless of the settings.
Initial value:
Initial value:
Wait Control Register 2 (WCR2)
R/W:
R/W:
Bit:
Bit:
Bit 14: A4WD0
0
1
0
1
A4WD1 A4WD0
R/W
15
—
0
7
0
R
R/W
14
—
0
6
0
R
Description
1 cycle
2 cycles
4 cycles
Reserved (do not set)
13
—
—
0
R
5
0
R
A4WM
R/W
12
—
0
4
0
R
A3WM
IW41
R/W
R/W
11
0
3
1
A2WM
IW40
R/W
R/W
10
0
2
0
A1WM
W41
R/W
R/W
9
0
1
1
(Initial value)
A0WM
W40
R/W
R/W
8
0
0
1
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