HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 522

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

Summary of BH Timing: Figure 11.43 is a summary of the BH output timing.
11.4
11.4.1
In this example data received by the serial communication interface (SCIF) with on-chip FIFO is
sent to external memory using DMAC channel 1. Table 11.9 lists the transfer conditions and
register setting values.
Table 11.9 Transfer Conditions and Register Setting Values for Data Transfer Between
Transfer Condition
Transfer source: SCFRDR1 in on-chip SCIF
Transfer destination: External memory (word space)
Number of transfers: 64
Transfer destination address: Increment
Transfer source address: Fixed
Bus mode: Cycle-steal
Transfer unit: Byte
DEI interrupt request at end of transfer DE = 1
Channel priority: Fixed (0 > 1) DME = 1
Transfer request source (transfer request signal): SCIF
(RXI)
Note: * Make sure the SCIF settings have interrupts enabled and the appropriate CPU interrupt
External
bus cycle
BH
level.
Usage Examples
Example of DMA Data Transfer Between On-chip SCIF and External Memory
On-chip SCIF and External Memory
CPU
DMAC
Figure 11.43 Summary of BH Output Timing
read 0
DMAC
read 1
DMAC
read 2
DMAC
read 3
Register
SAR1
DAR1
TCR1
CHCR1
DMAOR
DRCR1
DMAC
write 0
write 1
DMAC
Setting Value
H'FFFFFCCC
Transfer destination address
H'0040
H'4045
H'0001
H'05
write 2
DMAC
write 3
DMAC
CPU
507