HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 11

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

Section 9
9.1
9.2
9.3
9.4
Section 10 Ethernet Controller Direct Memory Access Controller
10.1 Overview............................................................................................................................ 411
10.2 Register Descriptions ......................................................................................................... 415
Overview............................................................................................................................ 371
9.1.1
9.1.2
9.1.3
9.1.4
Register Descriptions ......................................................................................................... 376
9.2.1
9.2.2
9.2.3
9.2.4
9.2.5
9.2.6
9.2.7
9.2.8
9.2.9
9.2.10 Collision Detect Counter Register (CDCR).......................................................... 387
9.2.11 Lost Carrier Counter Register (LCCR)................................................................. 388
9.2.12 Carrier Not Detect Counter Register (CNDCR) ................................................... 389
9.2.13 Illegal Frame Length Counter Register (IFLCR).................................................. 390
9.2.14 CRC Error Frame Counter Register (CEFCR) ..................................................... 391
9.2.15 Frame Receive Error Counter Register (FRECR ) ............................................... 392
9.2.16 Too-Short Frame Receive Counter Register (TSFRCR) ...................................... 393
9.2.17 Too-Long Frame Receive Counter Register (TLFRCR ) ..................................... 394
9.2.18 Residual-Bit Frame Counter Register (RFCR) ..................................................... 395
9.2.19 Multicast Address Frame Counter Register (MAFCR) ........................................ 396
Operation............................................................................................................................ 397
9.3.1
9.3.2
9.3.3
9.3.4
9.3.5
9.3.6
Connection to PHY-LSI..................................................................................................... 408
10.1.1 Features ................................................................................................................. 411
10.1.2 Configuration........................................................................................................ 412
10.1.3 Descriptor Management System ........................................................................... 413
10.1.4 Register Configuration.......................................................................................... 413
Ethernet Controller (EtherC)
Features ................................................................................................................. 371
Configuration........................................................................................................ 372
Pin Configuration.................................................................................................. 374
Ethernet Controller Register Configuration.......................................................... 375
EtherC Mode Register (ECMR)............................................................................ 376
Receive Frame Length Register (RFLR).............................................................. 379
EtherC Status Register (ECSR) ............................................................................ 380
EtherC Status Interrupt Permission Register (ECSIPR) ....................................... 381
PHY Interface Register (PIR) ............................................................................... 382
PHY Interface Status Register (PSR) ................................................................... 383
MAC Address High Register (MAHR) ................................................................ 384
MAC Address Low Register (MALR) ................................................................. 385
Tx Retry Over Counter Register (TROCR).......................................................... 386
Transmission ......................................................................................................... 397
Reception .............................................................................................................. 399
MII Frame Timing ................................................................................................ 401
Accessing MII Registers ....................................................................................... 403
Magic Packet™ Detection .................................................................................... 406
CPU Operating Mode and Ethernet Controller Operation.................................... 407
(E-DMAC)
........................................................................................................ 411
....................................................................... 371
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