HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 577

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

Bit 1: RDF
0
1
Note: SCFRDR is a 16-byte FIFO register. When RDF = 1, at least the receive trigger set number
Bit 0—Receive Data Ready (DR): Indicates that there are fewer than the receive trigger set
number of data bytes in the receive FIFO data register (SCFRDR), and no further data has arrived
for at least 15 etu after the stop bit of the last data received.
Bit 0: DR
0
1
Notes: 1. All remaining receive data should be read before clearing the DR flag.
564
of data bytes can be read. If all the data in SCFRDR is read and another read is performed,
the data value will be undefined. The number of receive data bytes in SCFRDR is indicated
by the lower 8 bits of SCFDR.
2. Equivalent to 1.5 frames when using an 8-bit, 1-stop-bit format.
etu: Elementary time unit = sec/bit
Description
The number of receive data bytes in SCFRDR is less than the receive trigger
set number
[Clearing conditions]
The number of receive data bytes in SCFRDR is equal to or greater than the
receive trigger set number
[Setting condition]
When SCFRDR contains at least the receive trigger set number of receive data
bytes
Description
Reception is in progress or has ended normally and there is no receive data
left in SCFRDR
[Clearing conditions]
No further receive data has arrived, and SCFRDR contains fewer than the
receive trigger set number of data bytes
[Setting condition]
When SCFRDR contains fewer than the receive trigger set number of receive
data bytes, and no further data has arrived for at least 15 etu after the stop bit
of the last data received*
In a reset or in standby mode
When SCFRDR is read until the number of receive data bytes in SCFRDR
falls below the receive trigger set number, and 0 is written to RDF after
reading RDF = 1
When SCFRDR is read by the on-chip DMAC until the number of receive
data bytes in SCFRDR falls below the receive trigger set number
In a reset or in standby mode
When 0 is written to DR after all the remaining receive data has been
read*
1
(Initial value)
(Initial value)