HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 35

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HD6417615

Manufacturer Part Number
HD6417615
Description
Hardware Manual
Manufacturer
Hitachi Semiconductor
Datasheet

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Table 1.2
Type
Bus control
Pin Functions (cont)
Symbol
CAS
OE
DQMUU/
WE3
DQMUL/
WE2
DQMLU/
WE1
DQMLL/
WE0
CAS3
CAS2
CAS1
CAS0
CKE
REFOUT
RD/WR
BUSHiZ
BH
STATS0, 1
I/O
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
Output
Output
Name
Column
address strobe
Output enable
Highest byte
access
Second byte
access
Third byte
access
Lowest byte
access
Column address
strobe 3
Column address
strobe 2
Column address
strobe 1
Column address
strobe 0
Clock enable
Refresh out
Read/write
Bus high
impedance
Burst hint
Status
Function
Synchronous DRAM CAS signal
EDO DRAM output enable signal
Used in access in RAS down mode
SRAM/synchronous DRAM highest byte
select signal
SRAM/synchronous DRAM second byte
select signal
SRAM/synchronous DRAM third byte
select signal
SRAM/synchronous DRAM lowest byte
select signal
DRAM highest byte select signal
DRAM second byte select signal
DRAM third byte select signal
DRAM lowest byte select signal
Synchronous DRAM clock enable signal
Signal requesting refresh execution
when the bus is released
DRAM/synchronous DRAM write signal
Signal used in combination with WAIT
signal to place bus and strobe signals in
the high-impedance state without the
ending bus cycle
Asserted at the start of a DMA burst,
negated one bus cycle before the end of
the burst
CPU, DMAC, and E-DMAC status
information
17

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