HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 24

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

Table 1.1
Item
Bus state controller
(BSC)
6
Features (cont)
Specifications
Address space divided into five areas (CS0 to CS4, max. linear 32 Mbytes
each)
Cache
Refresh functions
Direct DRAM interface
Direct synchronous DRAM interface
Bus arbitration (BRLS, BGR)
Refresh counter can be used as interval timer
Memory types such as DRAM, synchronous DRAM, burst ROM, can
Two synchronous DRAM spaces (CS2, CS3); CS3 also supports
Bus width (8, 16, 32 bits) can be selected for each area
Wait state insertion control for each area
Control signal output for each area
Endian can be set for CS2 and CS4
Cache area/cache-through area selection by access address
Selection of write-through or write-back mode
CAS-before-RAS refreshing (auto refreshing) or self-refreshing
Refresh interval settable by means of refresh counter and clock select
Concentrated refreshing according to refresh count setting
Refresh request output possible (REFOUT)
Multiplexed row address/column address output
Fast page mode burst transfer and continuous access when reading
EDO mode
TP cycle generation to secure RAS precharge time
Multiplexed row address/column address output
Bank-active mode (valid for CS3 only)
Selection of burst read/single write mode or burst read/burst write
Interrupt request generated on compare match (CMI interrupt request
be specified for each area
DRAM
setting
(1, 2, 4, 6, 8)
mode
signal)