HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 398

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

Bit 0—Illegal Carrier Detection Interrupt Permission (ICDIP): Controls interrupt notification by
the Illegal Carrier Detection bit.
Bit 0: ICDIP
0
1
9.2.5
PIR provides a means of accessing PHY-LSI internal registers via the MII.
Bits 31 to 4—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 3— MII Management Data-In (MDI): Indicates the level of the MDIO pin.
Bit 2— MII Management Data-Out (MDO): Outputs the value set to this bit by the MDIO pin
when the MMD bit is 1.
Bit 1— MII Management Mode (MMD): Specifies the data read/write direction with respect to the
MII. Read direction is indicated by 0, and write direction by 1.
Bit 0— MII Management Data Clock (MDC): Outputs the value set to this bit by the MDC pin
and supplies the MII with the management data clock.
For the method of accessing MII registers, see section 9.3.3, Accessing MII Registers.
382
Initial value:
Initial value:
PHY Interface Register (PIR)
R/W:
R/W:
Bit:
Bit:
Description
Interrupt notification by ICD bit in ECSR is disabled
Interrupt notification by ICD bit in ECSR is enabled
31
—
—
0
R
7
0
R
30
—
—
0
R
6
0
R
29
—
—
0
R
5
0
R
. . .
. . .
. . .
. . .
—
4
0
R
MDI
11
—
0
R
3
*
R
MDO
R/W
10
—
0
R
2
0
MMD
R/W
—
9
0
R
1
0
(Initial value)
MDC
R/W
—
8
0
R
0
0