HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 504

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

In a longword access of a 16-bit external device (figure 11.16) or an 8-bit external device (figure
11.17), or a word access of an 8-bit external device (figure 11.18), the lower and upper addresses
are output 2 and 4 times in each DMAC access in order to align the data. For all of these
addresses, the acknowledge signal becomes valid simultaneous with the start of output and the
signal becomes invalid 0.5 cycles before the address output ends. When multiple addresses are
output in a single access to align data for synchronous DRAM, DRAM, or burst ROM, an
acknowledge signal is output to those addresses as well.
(Active high)
(Active high)
Address
Address
DACKn
DACKn
Clock
Clock
bus
bus
Figure 11.14 DACKn Output in Ordinary Space Accesses (AM = 0)
Figure 11.15 DACKn Output in Ordinary Space Accesses (AM = 1)
DMAC
read
CPU
Basic timing
Invalid
write
Basic timing
DMAC
read
DMAC
write
Invalid
write
0.5 cycles
DMAC
CPU
write
1 wait inserted
DMAC read
CPU
1 wait inserted
Invalid
write
T
1
DMAC read
T
DMAC write
W
T
2
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