HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 287

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

After an auto-refresh command is issued, a bank active command is not issued for TRAS cycles,
regardless of the TRP bit setting. For synchronous DRAM, there is no RAS assertion period, but
there is a limit for the time from the issue of a refresh command until the next access. This value is
set to observe this limit. Commands are not issued for TRAS cycles when self-refresh is cleared.
Bit 12: TRAS1
0
1
Bit 10—Burst Enable (BE)
Bit 10: BE
0
1
Bit 9—Bank Active Mode (RASD)
Bit 9: RASD
0
1
270
Bit 11: TRAS0
0
1
0
1
Description
Burst disabled
High-speed page mode during DRAM and ED0 interfacing is enabled
Burst access conditions are as follows:
During synchronous DRAM access, burst operation is always enabled
regardless of this bit
Description
For DRAM, RAS is negated after access ends (normal operation)
For synchronous DRAM, a read or write is performed using auto-precharge
mode The next access always starts with a bank active command
For DRAM, after access ends RAS down mode is entered in which RAS is left
asserted. When using this mode with an external device connected which
performs writes other than to DRAM, see section 7.6.5, Burst Access
For synchronous DRAM, access ends in the bank active state. This is only
valid for area 3. When area 2 is synchronous DRAM, the mode is always auto-
precharge
Longword access, cache fill access, or DMAC 16-byte transfer, with 16-bit
bus width
Cache fill access or DMAC 16-byte transfer, with 32-bit bus width
Description
3 cycles
4 cycles
6 cycles
9 cycles
(Initial value)
(Initial value)
(Initial value)