HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 509

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

When external memory is set as bank active synchronous DRAM, during a single read the
acknowledge signal is output across the read command, wait and read address when the row
address is the same as the previous address output (figure 11.24). When the row address is
different from the previous address, the acknowledge signal is output across the precharge, row
address, read command, wait and read address (figure 11.25). Since the synchronous DRAM read
has only burst mode, during a single read an invalid address is output; the acknowledge signal is
output on the same timing. At this time, the acknowledge signal is extended until the write address
is output after the invalid read.
494
(Active high)
(Active high)
Address
Address
DACKn
DACKn
Clock
Clock
bus
bus
Figure 11.24 DACKn Output in Synchronous DRAM Single Read
Figure 11.25 DACKn Output in Synchronous DRAM Single Read
CPU
CPU
(Bank Active, Different Row Address, AM = 0)
(Bank Active, Same Row Address, AM = 0)
charge
command
Pre-
Read
address
Row
DMAC read (basic timing)
Read
command
Read
(basic timing)
DMAC read
Read
Invalid read
Invalid read
address
DMAC write (basic timing)
Row
address
Column
address
(basic timing)
Row
DMAC write
address
Column