HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 150

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

4.3.2
When an address error occurs, address error exception handling begins after the end of the bus
cycle in which the error occurred and completion of the executing instruction. The CPU operates
as follows:
1. The status register (SR) is saved to the stack.
2. The program counter (PC) is saved to the stack. The PC value saved is the start address of the
3. The exception service routine start address is fetched from the exception vector table entry that
Note: The same vector number, 10, is generated for a DMAC DMA address error and an E-
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instruction to be executed after the last instruction executed .
corresponds to the address error that occurred, and the program starts executing from that
address. The jump that occurs is not a delayed branch.
DMAC DMA address error. (See table 4.3 (a).)
Both the address error flag (AE) in the DMAC’s DMA operation register (DMAOR) and
the address error control bit (AEC) in the E-DMAC’s E-DMAC operation control register
(EDOCR) must therefore be read in the exception service routine to determine which
DMA address error has occurred.
Address Error Exception Handling