HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 397

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

Bit 0: ICD
0
1
Note: If a change in the signal input from the PHY-LSI occurs before the software recognition
9.2.4
This register enables or disables the interrupt sources indicated by the EtherC status register. Each
bit in this register enables or disables the interrupt indicated by the corresponding bit in the EtherC
status register.
Bits 31 to 3—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 2— LINK Signal Changed Interrupt Permission (LCHNGIP): Controls interrupt notification
by the LINK Signal Changed bit.
Bit 2: LCHNGIP
0
1
Bit 1—Magic Packet Detection Interrupt Permission (MPDIP): Controls interrupt notification by
the Magic Packet Detection bit.
Bit 1: MPDIP
0
1
Initial value:
Initial value:
period, the correct information may not be obtained. Refer to the timing specification for the
PHY-LSI used.
EtherC Status Interrupt Permission Register (ECSIPR)
R/W:
R/W:
Bit:
Bit:
Description
PHY-LSI has not detected an illegal carrier on the line
PHY-LSI has detected an illegal carrier on the line
Description
Interrupt notification by LCHNG bit in ECSR is disabled
Interrupt notification by LCHNG bit in ECSR is enabled
Description
Interrupt notification by MPD bit in ECSR is disabled
Interrupt notification by MPD bit in ECSR is enabled
31
—
—
0
R
7
0
R
30
—
—
0
R
6
0
R
29
—
—
0
R
5
0
R
. . .
. . .
. . .
. . .
—
4
0
R
11
—
—
0
R
3
0
R
LCHNGIP MPDIP
R/W
10
—
0
R
2
0
R/W
—
9
0
R
1
0
(Initial value)
(Initial value)
(Initial value)
ICDIP
R/W
—
8
0
R
0
0
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