HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 17

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

Section 19 I/O Ports
19.1 Overview............................................................................................................................ 755
19.2 Port A ................................................................................................................................. 755
19.3 Port B ................................................................................................................................. 757
Section 20 Power-Down Modes
20.1 Overview............................................................................................................................ 759
20.2 Register Descriptions ......................................................................................................... 761
20.3 Sleep Mode ........................................................................................................................ 765
20.4 Standby Mode .................................................................................................................... 765
20.5 Module Standby Function.................................................................................................. 771
Section 21 Electrical Characteristics
21.1 Absolute Maximum Ratings .............................................................................................. 773
21.2 DC Characteristics ............................................................................................................. 774
21.3 AC Characteristics ............................................................................................................. 776
18.3.1 Port A Control Register (PACR) .......................................................................... 743
18.3.2 Port A I/O Register (PAIOR)................................................................................ 746
18.3.3 Port B Control Registers (PBCR, PBCR2) ........................................................... 747
18.3.4 Port B I/O Register (PBIOR)................................................................................ 753
19.2.1 Register Configuration.......................................................................................... 756
19.2.2 Port A Data Register (PADR)............................................................................... 756
19.3.1 Register Configuration.......................................................................................... 757
19.3.2 Port B Data Register (PBDR) ............................................................................... 758
20.1.1 Power-Down Modes ............................................................................................. 759
20.1.2 Register ................................................................................................................. 760
20.2.1 Standby Control Register 1 (SBYCR1)................................................................ 761
20.2.2 Standby Control Register 2 (SBYCR2)................................................................ 763
20.3.1 Transition to Sleep Mode...................................................................................... 765
20.3.2 Canceling Sleep Mode.......................................................................................... 765
20.4.1 Transition to Standby Mode.................................................................................. 765
20.4.2 Canceling Standby Mode...................................................................................... 767
20.4.3 Standby Mode Cancellation by NMI Interrupt ..................................................... 767
20.4.4 Clock Pause Function ........................................................................................... 768
20.4.5 Notes on Standby Mode........................................................................................ 771
20.5.1 Transition to Module Standby Function ............................................................... 771
20.5.2 Clearing the Module Standby Function................................................................ 771
21.3.1 Clock Timing ........................................................................................................ 777
21.3.2 Control Signal Timing .......................................................................................... 781
21.3.3 Bus Timing ........................................................................................................... 783
21.3.4 Direct Memory Access Controller Timing ........................................................... 820
21.3.5 Free-Running Timer Timing ................................................................................ 821
............................................................................................................. 755
...................................................................................... 759
.............................................................................. 773
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