HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 286

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

Bit 1: TRP1
0
1
Bits 0 and 14—RAS-CAS Delay (RCD1, RCD0): When DRAM is connected, specifies the
number of cycles after RAS is asserted before CAS is asserted. When synchronous DRAM is
connected, specifies the number of cycles after a bank active (ACTV) command is issued until a
read or write command (READ, READA, WRIT, WRITA) is issued.
Bit 0: RCD1
0
1
Bits 8 and 13—Write-Precharge Delay (TRWL1, TRWL0): When the synchronous DRAM is not
in the bank active mode, this bit specifies the number of cycles after the write cycle before the
start-up of the auto-precharge. Based on this number of cycles, the timing at which the next active
command can be issued is calculated within the bus controller. In bank active mode, this bit
specifies the number of cycles before the precharge command is issued after the write command is
issued. This bit is ignored when memory other than synchronous DRAM is connected.
Bit 8: TRWL1
0
1
Bits 12 and 11—CAS-Before-RAS Refresh RAS Assert Time (TRAS1, TRAS0): These bits
specify the RAS assertion width when DRAM is connected.
Bit 12: TRAS1
0
1
Bit 15: TRP0
0
1
0
1
Bit 14: RCD0
0
1
0
1
Bit 13: TRWL0
0
1
0
1
Bit 11: TRAS0
0
1
0
1
Description
1 cycle
2 cycles
Reserved (do not set)
Reserved (do not set)
Description
1 cycle
2 cycles
3 cycles
Reserved (do not set)
Description
1 cycle
2 cycles
3 cycles
Reserved (do not set)
Description
2 cycles
3 cycles
4 cycles
5 cycles
(Initial value)
(Initial value)
(Initial value)
(Initial value)
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