HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 780

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

Figure 20.3 shows the clock pause function timing chart when the PLL circuit is halted.
The clock pause state can be canceled by means of NMI input, in the same way as the normal
standby state. The clock pause request should be canceled within four CKIO clock cycles after
NMI input. Figure 20.4 shows the timing chart for clock pause state cancellation by means of NMI
input (in the case of rising edge detection).
770
CKIO input
CKM input
CKPREQ/
CKIO input
NMI input
CKM input
CKPACK
CKPREQ/
CKPACK
output
output
Figure 20.4 Clock Pause Function Timing Chart (Cancellation by NMI Input)
Figure 20.3 Clock Pause Function Timing Chart (PLL Circuit 1 Halted)
Clock pause
acceptance
processing
Clock pause
acceptance
processing
Frequency
modification
Frequency
modification
NMI interrupt
Clock pause request
cancellation
Clock pause state
Clock pause state
Max. 4 cycles
Clock pause request
cancellation
Normal state
Normal state